Let me explain a little about Lenz factory testing. It has evolved over time. We evolved it for self preservation. Lenz GmbH took a lot of criticism several years back for developing a decoder which we thought met the Standards and RPs, but it could not be programmed by one of fellow NMRA DCC manufacturer's systems. Out of this grew our internal testing program that is still evolving.
Each and every new decoder hardware and software version is run against the official NMRA automated standards test in the factory. We do not run it against all the variations that the NMRA does, but we do test it completely. Our goal is 100% passage of all these tests before we go to production. At first we only performed the test on major revisions but we found that a simple program change led to an unexpected problem with one of our fellow DCC manufacturer's systems. These tests are now a routine part of every decoder development. As a result our decoders pass these tests all the time without any problem when we submit them to the NMRA.
Next we perform the RP tests. The scripts for these tests take a lot of manual time to perform and we find that most of our errors crop up in this area. Our goal is to pass the formal NMRA tests the first time through. Unfortunately, we have yet to succeed with this goal. Each and every time we submit a new decoder to the NMRA a new problem is found. These problems are normally with the RPs and often are in areas we simply did not expect. While this is frustrating, it simply points out that our internal testing continues to need improvement. We are working with the NMRA to refine these tests in order to improve them even further. Why? Because if we find a problem in testing it is a lot easier to fix than finding the problem post-production.
We want you the consumer to not have to worry if our decoders will work or if you will have problems with using them on your DCC system. It is our responsibility as a manufacturer to test our products and test them throughly.
In addition to testing with the NMRA we also beta test our products with as many different systems on real layouts as possible. These tests are also important as sometimes problems show up where we did not expect them. Finding and fixing a problem early sure beats trying to fix a problem after product release.
We also test each and every decoder that leaves the factory. Again this is self preservation. We fully warrant our product and we found that without these tests, mistakes happened. This means that you do not have to worry about performing complicated decoder tests prior to installation. Simply install the decoder and check out your installation on a programming track before operating your locomotive.
This testing process takes time and yes it does delay product release. But it greatly reduces the stress level after product release which is why we go to these lengths with testing. It is simply good business to focus on quality.
Some have raised the question on time to perform the NMRA tests and implied that the process is lengthly. We must disagree with this assessment. Yes it is true that we must check often with the volunteers on the testing status, as sometimes communication problems occur and most often they are caused by us. While all testing times can improve, we are generally pleased with the testing approach. As for having an independent testing agency perform the tests, we do not think this is a good idea. The purpose of these tests is to find errors and we much prefer having people who try to find the problems rather than a test lab who does not understand our unique problems nand whose job is simply to pass a product through a canned series of tests.
I recently went to a lab for a FCC test. It cost $1300 and a day of my time. It did not show us anything we did not know as they performed the same tests we had done in Europe. NMRA DCC testing takes considerably longer and we do not see a benefit of paying a test lab to simply redo a canned series of tests.
We believe DCC testing is an area where the NMRA is doing a good job. It is a fair process where no manufacturer has any advantage or disadvantage over any other. We support the NMRA in this venture and will continue to help them improve the tests even further.
Following are example test results from a typical decoder test run performed by the NMRA. I can not explain what all the results mean except that our decoders pass ALL tests 100%! That is a number I can understand. What this means to you the consumer is that our decoders fully implement the NMRA Standards and RPs and our packet reception remains at 100% across all bit timings even when subjected to noise. Its just another example of the high level of quality that goes into each and everyone of our products. Its a claim that no other manufacturer can make at this time.
Baseline Standard Test Results
RP Test Results
What does this mean to you the consumer?
Please note the start and end times on the following tests. Note that these are automated tests and run continuously over the time period. At 180 packets a second, thats sure a lot of packets transmitted and our decoder successfully received them all.
<Sat Mar 27 08:18:01 1999> STATUS BEGINNING
decoder test log
<Sat Mar 27 08:18:01 1999> STATUS Test software version B.2.15
Manufacturer: Lenz
Model number: LE105XF
Serial number: 3/19/99
--------------------------------
Noise injecting booster.
Level 6.1 Volts (Soar meter)
Rise/Fall 5/5 2 Volts/usec
25% noise at 100 KHz
normal leads
--------------------------------
<Sat Mar 27 08:19:05 1999> STATUS Starting decoder tests, address 3, type L
<Sat Mar 27 08:19:05 1999> STATUS Beginning self tests
<Sat Mar 27 08:19:10 1999> STATUS Self tests passed
<Sat Mar 27 08:19:10 1999> STATUS PC high 100( 17), low 100( 19)
<Sat Mar 27 08:19:10 1999> STATUS PC 1 usec delay 1
<Sat Mar 27 08:19:10 1999> STATUS Starting Decoder test cycle 1
<Sat Mar 27 08:19:12 1999> STATUS Margin test for 1T clock, 10 preambles
1T Margin: Minimum 1T 73, Maximum 1T 137
<Sat Mar 27 08:35:15 1999> STATUS Duty cycle test for 1 clock, 10 preambles
1H Duty: Min 1H -10, Max 1H >= 29 from 58 nominal
<Sat Mar 27 08:49:20 1999> STATUS Starting clock <All nominal>
- Clock 0T 200, 0H 100, 1T 116
Ramp: Tests 8; Passes 8, 100%
pre 10 idle 1: Tests 100; Passes 100, 100%
pre 10 idle 2: Tests 100; Passes 100, 100%
pre 12 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 2: Tests 100; Passes 100, 100%
Addr: Tests 253; Passes 253, 100%
Bad bit: Tests 39; Passes 39, 100%
0T 200 0H 100: Tests 100; Passes 100, 100%
0T 12000 0H 100: Tests 100; Passes 100, 100%
0T 12000 0H 11900: Tests 100; Passes 100, 100%
<Sat Mar 27 09:15:03 1999> STATUS Starting clock <All 1/4 fast>
- Clock 0T 196, 0H 98, 1T 113
Ramp: Tests 8; Passes 8, 100%
pre 10 idle 1: Tests 100; Passes 100, 100%
pre 10 idle 2: Tests 100; Passes 100, 100%
pre 12 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 2: Tests 100; Passes 100, 100%
Addr: Tests 253; Passes 253, 100%
Bad bit: Tests 39; Passes 39, 100%
0T 196 0H 98: Tests 100; Passes 100, 100%
0T 11996 0H 98: Tests 100; Passes 100, 100%
0T 11996 0H 11898: Tests 100; Passes 100, 100%
<Sat Mar 27 09:40:43 1999> STATUS Starting clock <Command station min>
- Clock 0T 190, 0H 95, 1T 110
Ramp: Tests 8; Passes 8, 100%
pre 10 idle 1: Tests 100; Passes 100, 100%
pre 10 idle 2: Tests 100; Passes 100, 100%
pre 12 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 2: Tests 100; Passes 100, 100%
Addr: Tests 253; Passes 253, 100%
Bad bit: Tests 39; Passes 39, 100%
0T 190 0H 95: Tests 100; Passes 100, 100%
0T 11990 0H 95: Tests 100; Passes 100, 100%
0T 11990 0H 11895: Tests 100; Passes 100, 100%
<Sat Mar 27 10:06:26 1999> STATUS Starting clock <Decoder minimum>
- Clock 0T 180, 0H 90, 1T 104
Ramp: Tests 8; Passes 8, 100%
pre 10 idle 1: Tests 100; Passes 100, 100%
pre 10 idle 2: Tests 100; Passes 100, 100%
pre 12 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 2: Tests 100; Passes 100, 100%
Addr: Tests 253; Passes 253, 100%
Bad bit: Tests 39; Passes 39, 100%
0T 180 0H 90: Tests 100; Passes 100, 100%
0T 11980 0H 90: Tests 100; Passes 100, 100%
0T 11980 0H 11890: Tests 100; Passes 100, 100%
<Sat Mar 27 10:31:55 1999> STATUS Starting clock <All 1/4 slow>
- Clock 0T 204, 0H 102, 1T 119
Ramp: Tests 8; Passes 8, 100%
pre 10 idle 1: Tests 100; Passes 100, 100%
pre 10 idle 2: Tests 100; Passes 100, 100%
pre 12 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 2: Tests 100; Passes 100, 100%
Addr: Tests 253; Passes 253, 100%
Bad bit: Tests 39; Passes 39, 100%
0T 204 0H 102: Tests 100; Passes 100, 100%
0T 12000 0H 102: Tests 100; Passes 100, 100%
0T 12000 0H 11898: Tests 100; Passes 100, 100%
<Sat Mar 27 10:58:00 1999> STATUS Starting clock <Command station max>
- Clock 0T 210, 0H 105, 1T 122
Ramp: Tests 8; Passes 8, 100%
pre 10 idle 1: Tests 100; Passes 100, 100%
pre 10 idle 2: Tests 100; Passes 100, 100%
pre 12 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 2: Tests 100; Passes 100, 100%
Addr: Tests 253; Passes 253, 100%
Bad bit: Tests 39; Passes 39, 100%
0T 210 0H 105: Tests 100; Passes 100, 100%
0T 12000 0H 105: Tests 100; Passes 100, 100%
0T 12000 0H 11895: Tests 100; Passes 100, 100%
<Sat Mar 27 11:23:55 1999> STATUS Starting clock <Decoder maximum>
- Clock 0T 220, 0H 110, 1T 128
Ramp: Tests 8; Passes 8, 100%
pre 10 idle 1: Tests 100; Passes 100, 100%
pre 10 idle 2: Tests 100; Passes 100, 100%
pre 12 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 2: Tests 100; Passes 100, 100%
Addr: Tests 253; Passes 253, 100%
Bad bit: Tests 39; Passes 39, 100%
0T 220 0H 110: Tests 100; Passes 100, 100%
0T 12000 0H 110: Tests 100; Passes 100, 100%
0T 12000 0H 11890: Tests 100; Passes 100, 100%
<Sat Mar 27 11:50:15 1999> STATUS Starting clock <Negative stretched 0>
- Clock 0T 300, 0H 100, 1T 116
Ramp: Tests 8; Passes 8, 100%
pre 10 idle 1: Tests 100; Passes 100, 100%
pre 10 idle 2: Tests 100; Passes 100, 100%
pre 12 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 2: Tests 100; Passes 100, 100%
Addr: Tests 253; Passes 253, 100%
Bad bit: Tests 39; Passes 39, 100%
0T 300 0H 100: Tests 100; Passes 100, 100%
0T 12000 0H 100: Tests 100; Passes 100, 100%
0T 12000 0H 11800: Tests 100; Passes 100, 100%
<Sat Mar 27 12:17:04 1999> STATUS Starting clock <Positive stretched 0>
- Clock 0T 300, 0H 200, 1T 116
Ramp: Tests 8; Passes 8, 100%
pre 10 idle 1: Tests 100; Passes 100, 100%
pre 10 idle 2: Tests 100; Passes 100, 100%
pre 12 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 2: Tests 100; Passes 100, 100%
Addr: Tests 253; Passes 253, 100%
Bad bit: Tests 39; Passes 39, 100%
0T 300 0H 200: Tests 100; Passes 100, 100%
0T 12000 0H 200: Tests 100; Passes 100, 100%
0T 12000 0H 11900: Tests 100; Passes 100, 100%
<Sat Mar 27 12:43:53 1999> STATUS Starting clock <Very negative 0>
- Clock 0T 2560, 0H 100, 1T 116
Ramp: Tests 8; Passes 8, 100%
pre 10 idle 1: Tests 100; Passes 100, 100%
pre 10 idle 2: Tests 100; Passes 100, 100%
pre 12 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 2: Tests 100; Passes 100, 100%
Addr: Tests 253; Passes 253, 100%
Bad bit: Tests 39; Passes 39, 100%
0T 2560 0H 100: Tests 100; Passes 100, 100%
0T 12000 0H 100: Tests 100; Passes 100, 100%
0T 12000 0H 9540: Tests 100; Passes 100, 100%
<Sat Mar 27 13:49:32 1999> STATUS Starting clock <Very positive 0>
- Clock 0T 2560, 0H 2460, 1T 116
Ramp: Tests 8; Passes 8, 100%
pre 10 idle 1: Tests 100; Passes 100, 100%
pre 10 idle 2: Tests 100; Passes 100, 100%
pre 12 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 1: Tests 100; Passes 100, 100%
pre 15 idle 2: Tests 100; Passes 100, 100%
Addr: Tests 253; Passes 253, 100%
Bad bit: Tests 39; Passes 39, 100%
0T 2560 0H 2460: Tests 100; Passes 100, 100%
0T 12000 0H 2460: Tests 100; Passes 100, 100%
0T 12000 0H 11900: Tests 100; Passes 100, 100%
<Sat Mar 27 14:55:11 1999> STATUS Truncate clock
- Clock 0T 200, 0H 100, 1T 116
Pre 10 Frag 37: Tests 2; Passes 2, 100% *
Pre 10 Frag 36: Tests 2; Passes 2, 100%
Pre 10 Frag 35: Tests 2; Passes 2, 100%
Pre 10 Frag 34: Tests 2; Passes 2, 100%
Pre 10 Frag 33: Tests 2; Passes 2, 100%
Pre 10 Frag 32: Tests 2; Passes 2, 100%
Pre 10 Frag 31: Tests 2; Passes 2, 100%
Pre 10 Frag 30: Tests 2; Passes 2, 100%
Pre 10 Frag 29: Tests 2; Passes 2, 100%
Pre 10 Frag 28: Tests 2; Passes 2, 100% *
Pre 10 Frag 27: Tests 2; Passes 2, 100%
Pre 10 Frag 26: Tests 2; Passes 2, 100%
Pre 10 Frag 25: Tests 2; Passes 2, 100%
Pre 10 Frag 24: Tests 2; Passes 2, 100%
Pre 10 Frag 23: Tests 2; Passes 2, 100%
Pre 10 Frag 22: Tests 2; Passes 2, 100%
Pre 10 Frag 21: Tests 2; Passes 2, 100%
Pre 10 Frag 20: Tests 2; Passes 2, 100%
Pre 10 Frag 19: Tests 2; Passes 2, 100% *
Pre 10 Frag 18: Tests 2; Passes 2, 100%
Pre 10 Frag 17: Tests 2; Passes 2, 100%
Pre 10 Frag 16: Tests 2; Passes 2, 100%
Pre 10 Frag 15: Tests 2; Passes 2, 100%
Pre 10 Frag 14: Tests 2; Passes 2, 100%
Pre 10 Frag 13: Tests 2; Passes 2, 100%
Pre 10 Frag 12: Tests 2; Passes 2, 100%
Pre 10 Frag 11: Tests 2; Passes 2, 100%
Pre 10 Frag 10: Tests 2; Passes 2, 100% *
Pre 10 Frag 9: Tests 2; Passes 2, 100% *
Pre 10 Frag 8: Tests 2; Passes 2, 100% *
Pre 10 Frag 7: Tests 2; Passes 2, 100% *
Pre 10 Frag 6: Tests 2; Passes 2, 100% *
Pre 10 Frag 5: Tests 2; Passes 2, 100% *
Pre 10 Frag 4: Tests 2; Passes 2, 100% *
Pre 10 Frag 3: Tests 2; Passes 2, 100% *
Pre 10 Frag 2: Tests 2; Passes 2, 100% *
Pre 10 Frag 1: Tests 2; Passes 2, 100% *
Pre 10 Frag 0: Tests 2; Passes 2, 100% *
Pre 11 Frag 38: Tests 2; Passes 2, 100% *
Pre 11 Frag 37: Tests 2; Passes 2, 100%
Pre 11 Frag 36: Tests 2; Passes 2, 100%
Pre 11 Frag 35: Tests 2; Passes 2, 100%
Pre 11 Frag 34: Tests 2; Passes 2, 100%
Pre 11 Frag 33: Tests 2; Passes 2, 100%
Pre 11 Frag 32: Tests 2; Passes 2, 100%
Pre 11 Frag 31: Tests 2; Passes 2, 100%
Pre 11 Frag 30: Tests 2; Passes 2, 100%
Pre 11 Frag 29: Tests 2; Passes 2, 100% *
Pre 11 Frag 28: Tests 2; Passes 2, 100%
Pre 11 Frag 27: Tests 2; Passes 2, 100%
Pre 11 Frag 26: Tests 2; Passes 2, 100%
Pre 11 Frag 25: Tests 2; Passes 2, 100%
Pre 11 Frag 24: Tests 2; Passes 2, 100%
Pre 11 Frag 23: Tests 2; Passes 2, 100%
Pre 11 Frag 22: Tests 2; Passes 2, 100%
Pre 11 Frag 21: Tests 2; Passes 2, 100%
Pre 11 Frag 20: Tests 2; Passes 2, 100% *
Pre 11 Frag 19: Tests 2; Passes 2, 100%
Pre 11 Frag 18: Tests 2; Passes 2, 100%
Pre 11 Frag 17: Tests 2; Passes 2, 100%
Pre 11 Frag 16: Tests 2; Passes 2, 100%
Pre 11 Frag 15: Tests 2; Passes 2, 100%
Pre 11 Frag 14: Tests 2; Passes 2, 100%
Pre 11 Frag 13: Tests 2; Passes 2, 100%
Pre 11 Frag 12: Tests 2; Passes 2, 100%
Pre 11 Frag 11: Tests 2; Passes 2, 100% *
Pre 11 Frag 10: Tests 2; Passes 2, 100% *
Pre 11 Frag 9: Tests 2; Passes 2, 100% *
Pre 11 Frag 8: Tests 2; Passes 2, 100% *
Pre 11 Frag 7: Tests 2; Passes 2, 100% *
Pre 11 Frag 6: Tests 2; Passes 2, 100% *
Pre 11 Frag 5: Tests 2; Passes 2, 100% *
Pre 11 Frag 4: Tests 2; Passes 2, 100% *
Pre 11 Frag 3: Tests 2; Passes 2, 100% *
Pre 11 Frag 2: Tests 2; Passes 2, 100% *
Pre 11 Frag 1: Tests 2; Passes 2, 100% *
Pre 11 Frag 0: Tests 2; Passes 2, 100% *
Pre 12 Frag 39: Tests 2; Passes 2, 100% *
Pre 12 Frag 38: Tests 2; Passes 2, 100%
Pre 12 Frag 37: Tests 2; Passes 2, 100%
Pre 12 Frag 36: Tests 2; Passes 2, 100%
Pre 12 Frag 35: Tests 2; Passes 2, 100%
Pre 12 Frag 34: Tests 2; Passes 2, 100%
Pre 12 Frag 33: Tests 2; Passes 2, 100%
Pre 12 Frag 32: Tests 2; Passes 2, 100%
Pre 12 Frag 31: Tests 2; Passes 2, 100%
Pre 12 Frag 30: Tests 2; Passes 2, 100% *
Pre 12 Frag 29: Tests 2; Passes 2, 100%
Pre 12 Frag 28: Tests 2; Passes 2, 100%
Pre 12 Frag 27: Tests 2; Passes 2, 100%
Pre 12 Frag 26: Tests 2; Passes 2, 100%
Pre 12 Frag 25: Tests 2; Passes 2, 100%
Pre 12 Frag 24: Tests 2; Passes 2, 100%
Pre 12 Frag 23: Tests 2; Passes 2, 100%
Pre 12 Frag 22: Tests 2; Passes 2, 100%
Pre 12 Frag 21: Tests 2; Passes 2, 100% *
Pre 12 Frag 20: Tests 2; Passes 2, 100%
Pre 12 Frag 19: Tests 2; Passes 2, 100%
Pre 12 Frag 18: Tests 2; Passes 2, 100%
Pre 12 Frag 17: Tests 2; Passes 2, 100%
Pre 12 Frag 16: Tests 2; Passes 2, 100%
Pre 12 Frag 15: Tests 2; Passes 2, 100%
Pre 12 Frag 14: Tests 2; Passes 2, 100%
Pre 12 Frag 13: Tests 2; Passes 2, 100%
Pre 12 Frag 12: Tests 2; Passes 2, 100% *
Pre 12 Frag 11: Tests 2; Passes 2, 100% *
Pre 12 Frag 10: Tests 2; Passes 2, 100% *
Pre 12 Frag 9: Tests 2; Passes 2, 100% *
Pre 12 Frag 8: Tests 2; Passes 2, 100% *
Pre 12 Frag 7: Tests 2; Passes 2, 100% *
Pre 12 Frag 6: Tests 2; Passes 2, 100% *
Pre 12 Frag 5: Tests 2; Passes 2, 100% *
Pre 12 Frag 4: Tests 2; Passes 2, 100% *
Pre 12 Frag 3: Tests 2; Passes 2, 100% *
Pre 12 Frag 2: Tests 2; Passes 2, 100% *
Pre 12 Frag 1: Tests 2; Passes 2, 100% *
Pre 12 Frag 0: Tests 2; Passes 2, 100% *
Pre 13 Frag 40: Tests 2; Passes 2, 100% *
Pre 13 Frag 39: Tests 2; Passes 2, 100%
Pre 13 Frag 38: Tests 2; Passes 2, 100%
Pre 13 Frag 37: Tests 2; Passes 2, 100%
Pre 13 Frag 36: Tests 2; Passes 2, 100%
Pre 13 Frag 35: Tests 2; Passes 2, 100%
Pre 13 Frag 34: Tests 2; Passes 2, 100%
Pre 13 Frag 33: Tests 2; Passes 2, 100%
Pre 13 Frag 32: Tests 2; Passes 2, 100%
Pre 13 Frag 31: Tests 2; Passes 2, 100% *
Pre 13 Frag 30: Tests 2; Passes 2, 100%
Pre 13 Frag 29: Tests 2; Passes 2, 100%
Pre 13 Frag 28: Tests 2; Passes 2, 100%
Pre 13 Frag 27: Tests 2; Passes 2, 100%
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Pre 13 Frag 22: Tests 2; Passes 2, 100% *
Pre 13 Frag 21: Tests 2; Passes 2, 100%
Pre 13 Frag 20: Tests 2; Passes 2, 100%
Pre 13 Frag 19: Tests 2; Passes 2, 100%
Pre 13 Frag 18: Tests 2; Passes 2, 100%
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Pre 13 Frag 16: Tests 2; Passes 2, 100%
Pre 13 Frag 15: Tests 2; Passes 2, 100%
Pre 13 Frag 14: Tests 2; Passes 2, 100%
Pre 13 Frag 13: Tests 2; Passes 2, 100% *
Pre 13 Frag 12: Tests 2; Passes 2, 100% *
Pre 13 Frag 11: Tests 2; Passes 2, 100% *
Pre 13 Frag 10: Tests 2; Passes 2, 100% *
Pre 13 Frag 9: Tests 2; Passes 2, 100% *
Pre 13 Frag 8: Tests 2; Passes 2, 100% *
Pre 13 Frag 7: Tests 2; Passes 2, 100% *
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Pre 13 Frag 5: Tests 2; Passes 2, 100% *
Pre 13 Frag 4: Tests 2; Passes 2, 100% *
Pre 13 Frag 3: Tests 2; Passes 2, 100% *
Pre 13 Frag 2: Tests 2; Passes 2, 100% *
Pre 13 Frag 1: Tests 2; Passes 2, 100% *
Pre 13 Frag 0: Tests 2; Passes 2, 100% *
Pre 14 Frag 41: Tests 2; Passes 2, 100% *
Pre 14 Frag 40: Tests 2; Passes 2, 100%
Pre 14 Frag 39: Tests 2; Passes 2, 100%
Pre 14 Frag 38: Tests 2; Passes 2, 100%
Pre 14 Frag 37: Tests 2; Passes 2, 100%
Pre 14 Frag 36: Tests 2; Passes 2, 100%
Pre 14 Frag 35: Tests 2; Passes 2, 100%
Pre 14 Frag 34: Tests 2; Passes 2, 100%
Pre 14 Frag 33: Tests 2; Passes 2, 100%
Pre 14 Frag 32: Tests 2; Passes 2, 100% *
Pre 14 Frag 31: Tests 2; Passes 2, 100%
Pre 14 Frag 30: Tests 2; Passes 2, 100%
Pre 14 Frag 29: Tests 2; Passes 2, 100%
Pre 14 Frag 28: Tests 2; Passes 2, 100%
Pre 14 Frag 27: Tests 2; Passes 2, 100%
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Pre 14 Frag 25: Tests 2; Passes 2, 100%
Pre 14 Frag 24: Tests 2; Passes 2, 100%
Pre 14 Frag 23: Tests 2; Passes 2, 100% *
Pre 14 Frag 22: Tests 2; Passes 2, 100%
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Pre 14 Frag 20: Tests 2; Passes 2, 100%
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Pre 14 Frag 15: Tests 2; Passes 2, 100%
Pre 14 Frag 14: Tests 2; Passes 2, 100% *
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Pre 14 Frag 12: Tests 2; Passes 2, 100% *
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Pre 14 Frag 10: Tests 2; Passes 2, 100% *
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Pre 14 Frag 2: Tests 2; Passes 2, 100% *
Pre 14 Frag 1: Tests 2; Passes 2, 100% *
Pre 14 Frag 0: Tests 2; Passes 2, 100% *
<Sat Mar 27 15:03:17 1999> STATUS Prior test clock
- Clock 0T 200, 0H 100, 1T 116
<42 42 00> <pre 10> Tests 2; Passes 2, 100%
<42 42 00> <pre 11> Tests 2; Passes 2, 100%
<42 42 00> <pre 12> Tests 2; Passes 2, 100%
<42 42 00> <pre 13> Tests 2; Passes 2, 100%
<42 42 00> <pre 14> Tests 2; Passes 2, 100%
<42 42 00> <pre 15> Tests 2; Passes 2, 100%
<42 42 00> <pre 16> Tests 2; Passes 2, 100%
<42 42 00> <pre 17> Tests 2; Passes 2, 100%
<42 42 00> <pre 18> Tests 2; Passes 2, 100%
<42 42 00> <pre 19> Tests 2; Passes 2, 100%
<42 42 00> <pre 20> Tests 2; Passes 2, 100%
<42 42 00> 0<pre 18> Tests 2; Passes 2, 100%
<42 42 00> 0<pre 19> Tests 2; Passes 2, 100%
<42 42 00> 0<pre 20> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 10> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 11> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 12> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 13> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 14> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 15> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 16> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 17> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 18> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 19> Tests 2; Passes 2, 100%
<42 42 00>1 <pre 20> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 10> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 11> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 12> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 13> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 14> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 15> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 16> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 17> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 18> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 19> Tests 2; Passes 2, 100%
<42 42 00>1 0<pre 20> Tests 2; Passes 2, 100%
<42 43 01> <pre 10> Tests 2; Passes 2, 100%
<42 43 01> <pre 11> Tests 2; Passes 2, 100%
<42 43 01> <pre 12> Tests 2; Passes 2, 100%
<42 43 01> <pre 13> Tests 2; Passes 2, 100%
<42 43 01> <pre 14> Tests 2; Passes 2, 100%
<42 43 01> <pre 15> Tests 2; Passes 2, 100%
<42 43 01> <pre 16> Tests 2; Passes 2, 100%
<42 43 01> <pre 17> Tests 2; Passes 2, 100%
<42 43 01> <pre 18> Tests 2; Passes 2, 100%
<42 43 01> <pre 19> Tests 2; Passes 2, 100%
<42 43 01> <pre 20> Tests 2; Passes 2, 100%
<42 43 01> 0<pre 18> Tests 2; Passes 2, 100%
<42 43 01> 0<pre 19> Tests 2; Passes 2, 100%
<42 43 01> 0<pre 20> Tests 2; Passes 2, 100%
<42 43 01>1 <pre 10> Tests 2; Passes 2, 100%
<42 43 01>1 <pre 11> Tests 2; Passes 2, 100%
<42 43 01>1 <pre 12> Tests 2; Passes 2, 100%
<42 43 01>1 <pre 13> Tests 2; Passes 2, 100%
<42 43 01>1 <pre 14> Tests 2; Passes 2, 100%
<42 43 01>1 <pre 15> Tests 2; Passes 2, 100%
<42 43 01>1 <pre 16> Tests 2; Passes 2, 100%
<42 43 01>1 <pre 17> Tests 2; Passes 2, 100%
<42 43 01>1 <pre 18> Tests 2; Passes 2, 100%
<42 43 01>1 <pre 19> Tests 2; Passes 2, 100%
<42 43 01>1 <pre 20> Tests 2; Passes 2, 100%
<42 43 01>1 0<pre 10> Tests 2; Passes 2, 100%
<42 43 01>1 0<pre 11> Tests 2; Passes 2, 100%
<42 43 01>1 0<pre 12> Tests 2; Passes 2, 100%
<42 43 01>1 0<pre 13> Tests 2; Passes 2, 100%
<42 43 01>1 0<pre 14> Tests 2; Passes 2, 100%
<42 43 01>1 0<pre 15> Tests 2; Passes 2, 100%
<42 43 01>1 0<pre 16> Tests 2; Passes 2, 100%
<42 43 01>1 0<pre 17> Tests 2; Passes 2, 100%
<42 43 01>1 0<pre 18> Tests 2; Passes 2, 100%
<42 43 01>1 0<pre 19> Tests 2; Passes 2, 100%
<42 43 01>1 0<pre 20> Tests 2; Passes 2, 100%
<42 41 03> <pre 10> Tests 2; Passes 2, 100%
<42 41 03> <pre 11> Tests 2; Passes 2, 100%
<42 41 03> <pre 12> Tests 2; Passes 2, 100%
<42 41 03> <pre 13> Tests 2; Passes 2, 100%
<42 41 03> <pre 14> Tests 2; Passes 2, 100%
<42 41 03> <pre 15> Tests 2; Passes 2, 100%
<42 41 03> <pre 16> Tests 2; Passes 2, 100%
<42 41 03> <pre 17> Tests 2; Passes 2, 100%
<42 41 03> <pre 18> Tests 2; Passes 2, 100%
<42 41 03> <pre 19> Tests 2; Passes 2, 100%
<42 41 03> <pre 20> Tests 2; Passes 2, 100%
<42 41 03> 0<pre 18> Tests 2; Passes 2, 100%
<42 41 03> 0<pre 19> Tests 2; Passes 2, 100%
<42 41 03> 0<pre 20> Tests 2; Passes 2, 100%
<42 41 03>1 <pre 10> Tests 2; Passes 2, 100%
<42 41 03>1 <pre 11> Tests 2; Passes 2, 100%
<42 41 03>1 <pre 12> Tests 2; Passes 2, 100%
<42 41 03>1 <pre 13> Tests 2; Passes 2, 100%
<42 41 03>1 <pre 14> Tests 2; Passes 2, 100%
<42 41 03>1 <pre 15> Tests 2; Passes 2, 100%
<42 41 03>1 <pre 16> Tests 2; Passes 2, 100%
<42 41 03>1 <pre 17> Tests 2; Passes 2, 100%
<42 41 03>1 <pre 18> Tests 2; Passes 2, 100%
<42 41 03>1 <pre 19> Tests 2; Passes 2, 100%
<42 41 03>1 <pre 20> Tests 2; Passes 2, 100%
<42 41 03>1 0<pre 10> Tests 2; Passes 2, 100%
<42 41 03>1 0<pre 11> Tests 2; Passes 2, 100%
<42 41 03>1 0<pre 12> Tests 2; Passes 2, 100%
<42 41 03>1 0<pre 13> Tests 2; Passes 2, 100%
<42 41 03>1 0<pre 14> Tests 2; Passes 2, 100%
<42 41 03>1 0<pre 15> Tests 2; Passes 2, 100%
<42 41 03>1 0<pre 16> Tests 2; Passes 2, 100%
<42 41 03>1 0<pre 17> Tests 2; Passes 2, 100%
<42 41 03>1 0<pre 18> Tests 2; Passes 2, 100%
<42 41 03>1 0<pre 19> Tests 2; Passes 2, 100%
<42 41 03>1 0<pre 20> Tests 2; Passes 2, 100%
<42 45 07> <pre 10> Tests 2; Passes 2, 100%
<42 45 07> <pre 11> Tests 2; Passes 2, 100%
<42 45 07> <pre 12> Tests 2; Passes 2, 100%
<42 45 07> <pre 13> Tests 2; Passes 2, 100%
<42 45 07> <pre 14> Tests 2; Passes 2, 100%
<42 45 07> <pre 15> Tests 2; Passes 2, 100%
<42 45 07> <pre 16> Tests 2; Passes 2, 100%
<42 45 07> <pre 17> Tests 2; Passes 2, 100%
<42 45 07> <pre 18> Tests 2; Passes 2, 100%
<42 45 07> <pre 19> Tests 2; Passes 2, 100%
<42 45 07> <pre 20> Tests 2; Passes 2, 100%
<42 45 07> 0<pre 18> Tests 2; Passes 2, 100%
<42 45 07> 0<pre 19> Tests 2; Passes 2, 100%
<42 45 07> 0<pre 20> Tests 2; Passes 2, 100%
<42 45 07>1 <pre 10> Tests 2; Passes 2, 100%
<42 45 07>1 <pre 11> Tests 2; Passes 2, 100%
<42 45 07>1 <pre 12> Tests 2; Passes 2, 100%
<42 45 07>1 <pre 13> Tests 2; Passes 2, 100%
<42 45 07>1 <pre 14> Tests 2; Passes 2, 100%
<42 45 07>1 <pre 15> Tests 2; Passes 2, 100%
<42 45 07>1 <pre 16> Tests 2; Passes 2, 100%
<42 45 07>1 <pre 17> Tests 2; Passes 2, 100%
<42 45 07>1 <pre 18> Tests 2; Passes 2, 100%
<42 45 07>1 <pre 19> Tests 2; Passes 2, 100%
<42 45 07>1 <pre 20> Tests 2; Passes 2, 100%
<42 45 07>1 0<pre 10> Tests 2; Passes 2, 100%
<42 45 07>1 0<pre 11> Tests 2; Passes 2, 100%
<42 45 07>1 0<pre 12> Tests 2; Passes 2, 100%
<42 45 07>1 0<pre 13> Tests 2; Passes 2, 100%
<42 45 07>1 0<pre 14> Tests 2; Passes 2, 100%
<42 45 07>1 0<pre 15> Tests 2; Passes 2, 100%
<42 45 07>1 0<pre 16> Tests 2; Passes 2, 100%
<42 45 07>1 0<pre 17> Tests 2; Passes 2, 100%
<42 45 07>1 0<pre 18> Tests 2; Passes 2, 100%
<42 45 07>1 0<pre 19> Tests 2; Passes 2, 100%
<42 45 07>1 0<pre 20> Tests 2; Passes 2, 100%
<42 4d 0f> <pre 10> Tests 2; Passes 2, 100%
<42 4d 0f> <pre 11> Tests 2; Passes 2, 100%
<42 4d 0f> <pre 12> Tests 2; Passes 2, 100%
<42 4d 0f> <pre 13> Tests 2; Passes 2, 100%
<42 4d 0f> <pre 14> Tests 2; Passes 2, 100%
<42 4d 0f> <pre 15> Tests 2; Passes 2, 100%
<42 4d 0f> <pre 16> Tests 2; Passes 2, 100%
<42 4d 0f> <pre 17> Tests 2; Passes 2, 100%
<42 4d 0f> <pre 18> Tests 2; Passes 2, 100%
<42 4d 0f> <pre 19> Tests 2; Passes 2, 100%
<42 4d 0f> <pre 20> Tests 2; Passes 2, 100%
<42 4d 0f> 0<pre 18> Tests 2; Passes 2, 100%
<42 4d 0f> 0<pre 19> Tests 2; Passes 2, 100%
<42 4d 0f> 0<pre 20> Tests 2; Passes 2, 100%
<42 4d 0f>1 <pre 10> Tests 2; Passes 2, 100%
<42 4d 0f>1 <pre 11> Tests 2; Passes 2, 100%
<42 4d 0f>1 <pre 12> Tests 2; Passes 2, 100%
<42 4d 0f>1 <pre 13> Tests 2; Passes 2, 100%
<42 4d 0f>1 <pre 14> Tests 2; Passes 2, 100%
<42 4d 0f>1 <pre 15> Tests 2; Passes 2, 100%
<42 4d 0f>1 <pre 16> Tests 2; Passes 2, 100%
<42 4d 0f>1 <pre 17> Tests 2; Passes 2, 100%
<42 4d 0f>1 <pre 18> Tests 2; Passes 2, 100%
<42 4d 0f>1 <pre 19> Tests 2; Passes 2, 100%
<42 4d 0f>1 <pre 20> Tests 2; Passes 2, 100%
<42 4d 0f>1 0<pre 10> Tests 2; Passes 2, 100%
<42 4d 0f>1 0<pre 11> Tests 2; Passes 2, 100%
<42 4d 0f>1 0<pre 12> Tests 2; Passes 2, 100%
<42 4d 0f>1 0<pre 13> Tests 2; Passes 2, 100%
<42 4d 0f>1 0<pre 14> Tests 2; Passes 2, 100%
<42 4d 0f>1 0<pre 15> Tests 2; Passes 2, 100%
<42 4d 0f>1 0<pre 16> Tests 2; Passes 2, 100%
<42 4d 0f>1 0<pre 17> Tests 2; Passes 2, 100%
<42 4d 0f>1 0<pre 18> Tests 2; Passes 2, 100%
<42 4d 0f>1 0<pre 19> Tests 2; Passes 2, 100%
<42 4d 0f>1 0<pre 20> Tests 2; Passes 2, 100%
<42 5d 1f> <pre 10> Tests 2; Passes 2, 100%
<42 5d 1f> <pre 11> Tests 2; Passes 2, 100%
<42 5d 1f> <pre 12> Tests 2; Passes 2, 100%
<42 5d 1f> <pre 13> Tests 2; Passes 2, 100%
<42 5d 1f> <pre 14> Tests 2; Passes 2, 100%
<42 5d 1f> <pre 15> Tests 2; Passes 2, 100%
<42 5d 1f> <pre 16> Tests 2; Passes 2, 100%
<42 5d 1f> <pre 17> Tests 2; Passes 2, 100%
<42 5d 1f> <pre 18> Tests 2; Passes 2, 100%
<42 5d 1f> <pre 19> Tests 2; Passes 2, 100%
<42 5d 1f> <pre 20> Tests 2; Passes 2, 100%
<42 5d 1f> 0<pre 18> Tests 2; Passes 2, 100%
<42 5d 1f> 0<pre 19> Tests 2; Passes 2, 100%
<42 5d 1f> 0<pre 20> Tests 2; Passes 2, 100%
<42 5d 1f>1 <pre 10> Tests 2; Passes 2, 100%
<42 5d 1f>1 <pre 11> Tests 2; Passes 2, 100%
<42 5d 1f>1 <pre 12> Tests 2; Passes 2, 100%
<42 5d 1f>1 <pre 13> Tests 2; Passes 2, 100%
<42 5d 1f>1 <pre 14> Tests 2; Passes 2, 100%
<42 5d 1f>1 <pre 15> Tests 2; Passes 2, 100%
<42 5d 1f>1 <pre 16> Tests 2; Passes 2, 100%
<42 5d 1f>1 <pre 17> Tests 2; Passes 2, 100%
<42 5d 1f>1 <pre 18> Tests 2; Passes 2, 100%
<42 5d 1f>1 <pre 19> Tests 2; Passes 2, 100%
<42 5d 1f>1 <pre 20> Tests 2; Passes 2, 100%
<42 5d 1f>1 0<pre 10> Tests 2; Passes 2, 100%
<42 5d 1f>1 0<pre 11> Tests 2; Passes 2, 100%
<42 5d 1f>1 0<pre 12> Tests 2; Passes 2, 100%
<42 5d 1f>1 0<pre 13> Tests 2; Passes 2, 100%
<42 5d 1f>1 0<pre 14> Tests 2; Passes 2, 100%
<42 5d 1f>1 0<pre 15> Tests 2; Passes 2, 100%
<42 5d 1f>1 0<pre 16> Tests 2; Passes 2, 100%
<42 5d 1f>1 0<pre 17> Tests 2; Passes 2, 100%
<42 5d 1f>1 0<pre 18> Tests 2; Passes 2, 100%
<42 5d 1f>1 0<pre 19> Tests 2; Passes 2, 100%
<42 5d 1f>1 0<pre 20> Tests 2; Passes 2, 100%
<42 7d 3f> <pre 10> Tests 2; Passes 2, 100%
<42 7d 3f> <pre 11> Tests 2; Passes 2, 100%
<42 7d 3f> <pre 12> Tests 2; Passes 2, 100%
<42 7d 3f> <pre 13> Tests 2; Passes 2, 100%
<42 7d 3f> <pre 14> Tests 2; Passes 2, 100%
<42 7d 3f> <pre 15> Tests 2; Passes 2, 100%
<42 7d 3f> <pre 16> Tests 2; Passes 2, 100%
<42 7d 3f> <pre 17> Tests 2; Passes 2, 100%
<42 7d 3f> <pre 18> Tests 2; Passes 2, 100%
<42 7d 3f> <pre 19> Tests 2; Passes 2, 100%
<42 7d 3f> <pre 20> Tests 2; Passes 2, 100%
<42 7d 3f> 0<pre 18> Tests 2; Passes 2, 100%
<42 7d 3f> 0<pre 19> Tests 2; Passes 2, 100%
<42 7d 3f> 0<pre 20> Tests 2; Passes 2, 100%
<42 7d 3f>1 <pre 10> Tests 2; Passes 2, 100%
<42 7d 3f>1 <pre 11> Tests 2; Passes 2, 100%
<42 7d 3f>1 <pre 12> Tests 2; Passes 2, 100%
<42 7d 3f>1 <pre 13> Tests 2; Passes 2, 100%
<42 7d 3f>1 <pre 14> Tests 2; Passes 2, 100%
<42 7d 3f>1 <pre 15> Tests 2; Passes 2, 100%
<42 7d 3f>1 <pre 16> Tests 2; Passes 2, 100%
<42 7d 3f>1 <pre 17> Tests 2; Passes 2, 100%
<42 7d 3f>1 <pre 18> Tests 2; Passes 2, 100%
<42 7d 3f>1 <pre 19> Tests 2; Passes 2, 100%
<42 7d 3f>1 <pre 20> Tests 2; Passes 2, 100%
<42 7d 3f>1 0<pre 10> Tests 2; Passes 2, 100%
<42 7d 3f>1 0<pre 11> Tests 2; Passes 2, 100%
<42 7d 3f>1 0<pre 12> Tests 2; Passes 2, 100%
<42 7d 3f>1 0<pre 13> Tests 2; Passes 2, 100%
<42 7d 3f>1 0<pre 14> Tests 2; Passes 2, 100%
<42 7d 3f>1 0<pre 15> Tests 2; Passes 2, 100%
<42 7d 3f>1 0<pre 16> Tests 2; Passes 2, 100%
<42 7d 3f>1 0<pre 17> Tests 2; Passes 2, 100%
<42 7d 3f>1 0<pre 18> Tests 2; Passes 2, 100%
<42 7d 3f>1 0<pre 19> Tests 2; Passes 2, 100%
<42 7d 3f>1 0<pre 20> Tests 2; Passes 2, 100%
<02 7d 7f> <pre 10> Tests 2; Passes 2, 100%
<02 7d 7f> <pre 11> Tests 2; Passes 2, 100%
<02 7d 7f> <pre 12> Tests 2; Passes 2, 100%
<02 7d 7f> <pre 13> Tests 2; Passes 2, 100%
<02 7d 7f> <pre 14> Tests 2; Passes 2, 100%
<02 7d 7f> <pre 15> Tests 2; Passes 2, 100%
<02 7d 7f> <pre 16> Tests 2; Passes 2, 100%
<02 7d 7f> <pre 17> Tests 2; Passes 2, 100%
<02 7d 7f> <pre 18> Tests 2; Passes 2, 100%
<02 7d 7f> <pre 19> Tests 2; Passes 2, 100%
<02 7d 7f> <pre 20> Tests 2; Passes 2, 100%
<02 7d 7f> 0<pre 18> Tests 2; Passes 2, 100%
<02 7d 7f> 0<pre 19> Tests 2; Passes 2, 100%
<02 7d 7f> 0<pre 20> Tests 2; Passes 2, 100%
<02 7d 7f>1 <pre 10> Tests 2; Passes 2, 100%
<02 7d 7f>1 <pre 11> Tests 2; Passes 2, 100%
<02 7d 7f>1 <pre 12> Tests 2; Passes 2, 100%
<02 7d 7f>1 <pre 13> Tests 2; Passes 2, 100%
<02 7d 7f>1 <pre 14> Tests 2; Passes 2, 100%
<02 7d 7f>1 <pre 15> Tests 2; Passes 2, 100%
<02 7d 7f>1 <pre 16> Tests 2; Passes 2, 100%
<02 7d 7f>1 <pre 17> Tests 2; Passes 2, 100%
<02 7d 7f>1 <pre 18> Tests 2; Passes 2, 100%
<02 7d 7f>1 <pre 19> Tests 2; Passes 2, 100%
<02 7d 7f>1 <pre 20> Tests 2; Passes 2, 100%
<02 7d 7f>1 0<pre 10> Tests 2; Passes 2, 100%
<02 7d 7f>1 0<pre 11> Tests 2; Passes 2, 100%
<02 7d 7f>1 0<pre 12> Tests 2; Passes 2, 100%
<02 7d 7f>1 0<pre 13> Tests 2; Passes 2, 100%
<02 7d 7f>1 0<pre 14> Tests 2; Passes 2, 100%
<02 7d 7f>1 0<pre 15> Tests 2; Passes 2, 100%
<02 7d 7f>1 0<pre 16> Tests 2; Passes 2, 100%
<02 7d 7f>1 0<pre 17> Tests 2; Passes 2, 100%
<02 7d 7f>1 0<pre 18> Tests 2; Passes 2, 100%
<02 7d 7f>1 0<pre 19> Tests 2; Passes 2, 100%
<02 7d 7f>1 0<pre 20> Tests 2; Passes 2, 100%
<ff 00 ff> <pre 10> Tests 2; Passes 2, 100%
<ff 00 ff> <pre 11> Tests 2; Passes 2, 100%
<ff 00 ff> <pre 12> Tests 2; Passes 2, 100%
<ff 00 ff> <pre 13> Tests 2; Passes 2, 100%
<ff 00 ff> <pre 14> Tests 2; Passes 2, 100%
<ff 00 ff> <pre 15> Tests 2; Passes 2, 100%
<ff 00 ff> <pre 16> Tests 2; Passes 2, 100%
<ff 00 ff> <pre 17> Tests 2; Passes 2, 100%
<ff 00 ff> <pre 18> Tests 2; Passes 2, 100%
<ff 00 ff> <pre 19> Tests 2; Passes 2, 100%
<ff 00 ff> <pre 20> Tests 2; Passes 2, 100%
<ff 00 ff> 0<pre 18> Tests 2; Passes 2, 100%
<ff 00 ff> 0<pre 19> Tests 2; Passes 2, 100%
<ff 00 ff> 0<pre 20> Tests 2; Passes 2, 100%
<ff 00 ff>1 <pre 10> Tests 2; Passes 2, 100%
<ff 00 ff>1 <pre 11> Tests 2; Passes 2, 100%
<ff 00 ff>1 <pre 12> Tests 2; Passes 2, 100%
<ff 00 ff>1 <pre 13> Tests 2; Passes 2, 100%
<ff 00 ff>1 <pre 14> Tests 2; Passes 2, 100%
<ff 00 ff>1 <pre 15> Tests 2; Passes 2, 100%
<ff 00 ff>1 <pre 16> Tests 2; Passes 2, 100%
<ff 00 ff>1 <pre 17> Tests 2; Passes 2, 100%
<ff 00 ff>1 <pre 18> Tests 2; Passes 2, 100%
<ff 00 ff>1 <pre 19> Tests 2; Passes 2, 100%
<ff 00 ff>1 <pre 20> Tests 2; Passes 2, 100%
<ff 00 ff>1 0<pre 10> Tests 2; Passes 2, 100%
<ff 00 ff>1 0<pre 11> Tests 2; Passes 2, 100%
<ff 00 ff>1 0<pre 12> Tests 2; Passes 2, 100%
<ff 00 ff>1 0<pre 13> Tests 2; Passes 2, 100%
<ff 00 ff>1 0<pre 14> Tests 2; Passes 2, 100%
<ff 00 ff>1 0<pre 15> Tests 2; Passes 2, 100%
<ff 00 ff>1 0<pre 16> Tests 2; Passes 2, 100%
<ff 00 ff>1 0<pre 17> Tests 2; Passes 2, 100%
<ff 00 ff>1 0<pre 18> Tests 2; Passes 2, 100%
<ff 00 ff>1 0<pre 19> Tests 2; Passes 2, 100%
<ff 00 ff>1 0<pre 20> Tests 2; Passes 2, 100%
<Sat Mar 27 15:16:26 1999> STATUS 6 byte prior test clock
- Clock 0T 200, 0H 100, 1T 116
<42 61 61 61 61 42> <pre 10> Tests 2; Passes 2, 100%
<42 61 61 61 61 42> <pre 11> Tests 2; Passes 2, 100%
<42 61 61 61 61 42> <pre 12> Tests 2; Passes 2, 100%
<42 61 61 61 61 42> <pre 13> Tests 2; Passes 2, 100%
<42 61 61 61 61 42> <pre 14> Tests 2; Passes 2, 100%
<42 61 61 61 61 42> 0<pre 10> Tests 2; Passes 2, 100%
<42 61 61 61 61 42> 0<pre 11> Tests 2; Passes 2, 100%
<42 61 61 61 61 42> 0<pre 12> Tests 2; Passes 2, 100%
<42 61 61 61 61 42> 0<pre 13> Tests 2; Passes 2, 100%
<42 61 61 61 61 42> 0<pre 14> Tests 2; Passes 2, 100%
<42 61 61 61 61 42>1 <pre 10> Tests 2; Passes 2, 100%
<42 61 61 61 61 42>1 <pre 11> Tests 2; Passes 2, 100%
<42 61 61 61 61 42>1 <pre 12> Tests 2; Passes 2, 100%
<42 61 61 61 61 42>1 <pre 13> Tests 2; Passes 2, 100%
<42 61 61 61 61 42>1 <pre 14> Tests 2; Passes 2, 100%
<42 61 61 61 61 42>1 0<pre 10> Tests 2; Passes 2, 100%
<42 61 61 61 61 42>1 0<pre 11> Tests 2; Passes 2, 100%
<42 61 61 61 61 42>1 0<pre 12> Tests 2; Passes 2, 100%
<42 61 61 61 61 42>1 0<pre 13> Tests 2; Passes 2, 100%
<42 61 61 61 61 42>1 0<pre 14> Tests 2; Passes 2, 100%
<42 bd ff ff ff 00> <pre 10> Tests 2; Passes 2, 100%
<42 bd ff ff ff 00> <pre 11> Tests 2; Passes 2, 100%
<42 bd ff ff ff 00> <pre 12> Tests 2; Passes 2, 100%
<42 bd ff ff ff 00> <pre 13> Tests 2; Passes 2, 100%
<42 bd ff ff ff 00> <pre 14> Tests 2; Passes 2, 100%
<42 bd ff ff ff 00> 0<pre 10> Tests 2; Passes 2, 100%
<42 bd ff ff ff 00> 0<pre 11> Tests 2; Passes 2, 100%
<42 bd ff ff ff 00> 0<pre 12> Tests 2; Passes 2, 100%
<42 bd ff ff ff 00> 0<pre 13> Tests 2; Passes 2, 100%
<42 bd ff ff ff 00> 0<pre 14> Tests 2; Passes 2, 100%
<42 bd ff ff ff 00>1 <pre 10> Tests 2; Passes 2, 100%
<42 bd ff ff ff 00>1 <pre 11> Tests 2; Passes 2, 100%
<42 bd ff ff ff 00>1 <pre 12> Tests 2; Passes 2, 100%
<42 bd ff ff ff 00>1 <pre 13> Tests 2; Passes 2, 100%
<42 bd ff ff ff 00>1 <pre 14> Tests 2; Passes 2, 100%
<42 bd ff ff ff 00>1 0<pre 10> Tests 2; Passes 2, 100%
<42 bd ff ff ff 00>1 0<pre 11> Tests 2; Passes 2, 100%
<42 bd ff ff ff 00>1 0<pre 12> Tests 2; Passes 2, 100%
<42 bd ff ff ff 00>1 0<pre 13> Tests 2; Passes 2, 100%
<42 bd ff ff ff 00>1 0<pre 14> Tests 2; Passes 2, 100%
<42 bd 55 55 55 aa> <pre 10> Tests 2; Passes 2, 100%
<42 bd 55 55 55 aa> <pre 11> Tests 2; Passes 2, 100%
<42 bd 55 55 55 aa> <pre 12> Tests 2; Passes 2, 100%
<42 bd 55 55 55 aa> <pre 13> Tests 2; Passes 2, 100%
<42 bd 55 55 55 aa> <pre 14> Tests 2; Passes 2, 100%
<42 bd 55 55 55 aa> 0<pre 10> Tests 2; Passes 2, 100%
<42 bd 55 55 55 aa> 0<pre 11> Tests 2; Passes 2, 100%
<42 bd 55 55 55 aa> 0<pre 12> Tests 2; Passes 2, 100%
<42 bd 55 55 55 aa> 0<pre 13> Tests 2; Passes 2, 100%
<42 bd 55 55 55 aa> 0<pre 14> Tests 2; Passes 2, 100%
<42 bd 55 55 55 aa>1 <pre 10> Tests 2; Passes 2, 100%
<42 bd 55 55 55 aa>1 <pre 11> Tests 2; Passes 2, 100%
<42 bd 55 55 55 aa>1 <pre 12> Tests 2; Passes 2, 100%
<42 bd 55 55 55 aa>1 <pre 13> Tests 2; Passes 2, 100%
<42 bd 55 55 55 aa>1 <pre 14> Tests 2; Passes 2, 100%
<42 bd 55 55 55 aa>1 0<pre 10> Tests 2; Passes 2, 100%
<42 bd 55 55 55 aa>1 0<pre 11> Tests 2; Passes 2, 100%
<42 bd 55 55 55 aa>1 0<pre 12> Tests 2; Passes 2, 100%
<42 bd 55 55 55 aa>1 0<pre 13> Tests 2; Passes 2, 100%
<42 bd 55 55 55 aa>1 0<pre 14> Tests 2; Passes 2, 100%
<Sat Mar 27 15:18:53 1999> STATUS Packets sent 1843916, Bytes sent 14688041
<Sat Mar 27 15:18:53 1999> STATUS Tests COMPLETED, All tests passed
The NMRA performs a large series of functional tests on a decoder to ensure that it functions correctly when each bit sequence is sent to the decoder. The primary too for doing this is a packet script program that sends a specified sequence to the decoder while the results are observed. Following is an example of such a script. A complete listing of the decoder submital form together with a completed the test report t can be seen by reading the following PDF files.
LE105XF Test Results. (note we are awaiting a pdf version from the NMRA but will post it as soon as it is available.)
It means that our decoders faithfully follow the complete Standards and RPs. No matter which NMRA DCC command station you run our decoders on, they will work as well as if not better than the manufacturers of your command station native decoder. No hidden suprises, no excuses, no partial implementations, no compatibility problems!
We are very proud of our decoders and proud that they carry the NMRA conformance seal. Building a NMRA DCC decoder is easy. Building an NMRA DCC decoder that completely and faithfully complies to all the NMRA standards and RPs is much more difficult. It takes a lot of extra work to achive full NMRA conformance and it sure would be a lot easier to just release products without having them tested and having to correct the problems identified during the test. But releasing products that do not completely comply or are full of defects in against our company culture. We feel it our responsibility to provide you with the best product we can and testing is just part of good sound quality control.
We stress quality in our products and this is just one more way of demonstrating our committment fo multi-manufacturer compatible NMRA DCC model railroad control.
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This page was designed by Debbie Ames, owner tttrains